As efficient power management for handheld devices (e.g., smart phones) becomes crucial, entering and/or exiting power-down mode(s) become quite frequent. Today many processors use fine-grain power gating to reduce the leakage power of inactive circuit blocks by means of power gates (PGs). These PGs cause blocks of circuits to enter various power modes including destructive sleep. The term “destructive sleep” conventionally refers to a sleep mode where data in memory is lost because power supply level is dropped close to zero. To return to normal mode, data in the memory and other sequential logics (such as flip-flops and latches) may have to be restored from a secondary memory source, and this process lowers the overall performance of the computing system. For a constant power budget, the leakage savings (from destructive sleep) can be traded off for a performance gain. Unfortunately, conventional destructive sleep results in memory and flip-flop data loss, whereas data needs to be retained in a variety of sleep states. Further, fast wake-up of a gated power domain can lead to supply noise in neighboring circuits.